Many electronics systems use multiple voltage supplies to power semiconductor devices. To enable a device powered at one voltage level to interface with a device powered at a second voltage level, it is often desirable to use a circuit to shift between the voltage levels.
Two common level shifting techniques used today are shown in FIGS. 1A and 1B. The circuits provided and herein are illustrated with MOSFETs for the sake of simplicity. However, one of ordinary skill in the art would appreciate that other types of transistors would work in these circuits and that there are trade-offs associated with using the other types of transistors. FIG. 1A involves an n-channel input circuit and a cross coupled p-channel circuit. The p-channel circuit 104, 105 and buffer 106 operate within a higher voltage range, and buffer 101 operates at a lower voltage range and n-channel transistors 102, 103 transition between a lower and higher voltage range. N-channel transistors 102, 103 are high voltage transistors with the gates operating at the lower voltage range and the drains operating at the higher voltage range. Transistors 102, 103 communicate the signal from low voltage differential buffer 101 to the high voltage range circuitry while isolating the higher voltage range signal from the low voltage range differential buffer 101. When an input is applied to the n-channel transistors 102, 103, the n-channels 102, 103 turn on one of p-channels 104, 105. The cross coupled p-channel circuit latches in the value. The source of n-channel 103 and the drain of p-channel 105 pull the input to buffer 106 rail to rail. N-channel 103 can pull to ground, and p-channel 105 pulls to the higher voltage level. The lower voltage transistors could be destroyed if they are exposed to the higher voltage range.
As an example, apply a high level input voltage (for example 1.2V) at input A of differential output buffer inverter 101 in FIG. 1A. Also assume, for this example, that Dvdd is 1.2V and Avdd is 3.3V.
If A is high, pa goes to 1.2 volts and ma is substantially zero volts. Then pa turns on n-channel 102, because pa is higher than the turn-on threshold voltage (0.5 v) of n-channel 102 such that some current is drawn from drain to source.
As n-channel 102 turns on, ma is at substantially zero volts so n-channel 103 is turned off. When n-channel 102 is turned on and n-channel 103 is turned off, the drain of n-channel 102 is pulled down to a value near Gnd which will turn on p-channel 105 since a p-channel transistor turns on when the gate voltage is lower than the source. Meanwhile, n-channel 103 is off so that the drain impedance is very high. This causes the drain voltage of p-channel 105 and the input of buffer 106 to rise. Since p-channel 105 is on, p-channel 104 begins to be turned off.
If p-channels 104, 105 and n-channel 102, 103 are designed with the appropriate ratio, the drain of n-channel 102 will go to ground, and p-channel 105 will be turned on harder and harder. This will pull the drain of n-channel 103 higher and higher which sets p-channel 104 closer to off. Since the drain of n-channel 103 is not pulled low, p-channel 105 pulls the input of buffer 106 high.
The final steady state condition in this example has the drain of n-channel 102 at ground and the drain of n-channel 103 at Avdd of 3.3 volts. This signal is sent to buffer 106 which drives the output at Y to 3.3V.
Conversely, when A goes low to 0 volts, pa now is at ground, ma is at 1.2 volts and the circuit achieves the opposite result. N-channel 103 is dominant when n-channel 102 is turned off. The drain of n-channel 103 is pulled to ground and the output at Y is low.
This circuit generally works well because there is no situation where both p-channel 104 and n-channel 102, or p-channel 105 and n-channel 103 are on at the same time. So no “bias current” travels between Avdd to Gnd in a steady state condition. “Bias current” is an undesirable but necessary current associated with a circuit structure and is often independent of manufacturing process. “Leakage current,” on the other hand, is an undesirable current associated with a manufacturing process. Generally leakage current cannot be eliminated through circuit techniques.  There is zero bias power consumption in the steady state because no current is able to pass between the two voltage rails. There is still leakage current associated with the circuit in FIG. 1A; but this current is negligible in most applications.
A problem with this circuit is that since Dvdd and Avdd are from different voltage sources, they are usually derived from different circuitry. The operation of the circuit depends on n-channel 103 and p-channel 105 having the proper ratio. When n-channel 103 is switched on to turn p-channel 105 off, n-channel 103 has to be strong enough to overcome the previous latching of p-channel 104 and p-channel 105. The drive strength of n-channel 103 has to be able to overcome the drive strength of p-channel 105. To overcome p-channel 105, the gate of p-channel 104 will be pulled to ground which will turn on p-channel 104 and will pull the gate of p-channel 105 high, turning it off. To initiate this operation, n-channel 103 has to be able to overcome p-channel 105 when it is turned on. In the bias curves of a MOSFET transistor, the drive strength is related to its on-state resistance, which is based on its gate to source voltage.
The gate drive of p-channel 105 is at ground. Avdd is at 3.3 volts. The difference between those is 3.3 volts. That gate drive has to be counteracted by ma which is only 1.2 volts. So there is one transistor with a gate drive of 3.3 v and another transistor with a gate drive of 1.2 v.
Typically, the physical size of the transistor with the 1.2 v drive is increased such that it can overcome the 3.3 v drive due to the increased transistor area. Although the 1.2V-gate-driven n-channel transistor can be sized to compensate for a 3.3V-gate-driven p-channel transistor under typical conditions, the compensation may not be maintained as operating and manufacturing conditions vary. A supply voltage may vary up to 10%, and the 1.2 v supply will often vary independently from the 3.3 v supply. N-channel and p-channel devices are created from different materials and processes, and these different materials have temperature and manufacturing variations that are not correlated with one another. Furthermore, as variations from typical conditions arise, n-channel transistor and p-channel transistor mismatches introduce signal distortion due to unmatched rising and falling propagation delays.
A second circuit method for voltage level translation as shown in FIG. 1B involves a current mirror formed by p-channel 154 and p-channel 155. The gate of p-channel 154 is tied to the drain of p-channel 154, making it a diode connected transistor. The gates of p-channel 154 and p-channel 155 are also connected, so the current drawn through p-channel 154 provides the gate bias voltage for both p-channels 154 and 155. The sources of p-channels 154 and 155 are also tied to the same node (Avdd), and the transistors are the same size, same type, and have the same layout. Therefore, p-channel 155 will have the same drain current that p-channel 154 has.
Whenever n-channel 152 is on, its drive current also appears on p-channel 154 due to the series connection. Since p-channel 154 and p-channel 155 form a current mirror, the drive current of p-channel 155 matches that of n-channel 152. If n-channel 152 and n-channel 153 are also matched, the rising and falling currents that drive the input of buffer 156 will be matched.
The circuit in FIG. 1B is driven with the same differential low voltage circuit as in FIG. 1A. If signal A is high (1.2V), signal pa is at 1.2 volts and ma is at substantially zero volts. In this situation, n-channel 153 is off completely. The drain of p-channel 155 is pulled up to Avdd with a strength equal to that of n-channel 152. When the input switches state, n-channel 153 has the same strength as n-channel 152. When n-channel 152 is turned off, p-channel 155 has no drive and n-channel 153 can easily pull down to ground.
Because p-channel 155 will always have the same drive as n-channel 152 due to the p-channel current mirror, and since n-channel 152 and n-channel 153 can be easily matched with similar bias, layout geometry, and material construction, the rise and fall drive to buffer 156 is matched. Matching rise and fall drive eliminates distortion in the signal propagated from A to Y by providing matched rising and falling propagation delays.
Since p-channels 154 and 155 are both biased with reference to Avdd, the matching properties of the p-channel current mirror are independent of Avdd variation. Since both matched n-channels 152 and 153 are driven by Dvdd circuitry, their matching properties are independent of Dvdd. However, when n-channel 152 is on, steady-state bias current flows between transistors 152 and 154. Whereas the signal integrity features of the circuit of FIG. 1B are an improvement from those of the circuit in FIG. 1A, the steady-state bias current makes the circuit of FIG. 1B undesirable for low-power applications.
The circuit of FIG. 1A has zero-bias current, but mismatched rise and fall times on the output. The circuit of FIG. 1B has matched rise and fall times but high bias current.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.